发明名称 DATA PROCESSOR
摘要 PURPOSE:To reduce the number of circuits by performing positive number/ negative number conversion by outputting selectively inversion data to a multiplexer, and inputting selectively and outputting the output data of an adder circuit to the multiplexer by latching. CONSTITUTION:Data D0-Dm and the inversion data by inverters I0-Im are inputted to the multiplexer 1', and the output of the multiplexer and that of a decoder 4 are inputted to the adder circuit 3. And when the value of the input signal D of the decoder 4 is set at n(m+1>n>0, 1) is outputted to an output terminal at an (n+1)th bit counting from a highest order, and 0 to another output termi nal, respectively. And the output of the circuit 3 is latched at a register 5 corre sponding to a control signal E, then, it is inputted to the multiplexer 1', and either three input data of the multiplexer 1' is selected corresponding to a control signal C, and is inputted to the circuit 3.
申请公布号 JPH01184530(A) 申请公布日期 1989.07.24
申请号 JP19880010194 申请日期 1988.01.19
申请人 RICOH CO LTD 发明人 OTEGI SUGITAKA
分类号 G06F7/38 主分类号 G06F7/38
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