| 摘要 |
PURPOSE:To reduce a phase error by fetching receiving data by means of the timing clock of a digital PLL, simultaneously, detecting the change of the data, and controlling the phase of the digital PLL with the result of a slicing means at the time of detecting. CONSTITUTION:A control means 4 always detects a time when the change of the receiving data, namely, a purposed change such as the change of the value fetched by a reproducing clock from 1 to 0, is executed, and when the change is detected here, a comparison result with, for example, a level to be slightly low from an H level in a slicing means 2 is fetched. Since the reproducing clock is advanced when a receiving data level is higher than the level from the slicing means 2 at such a time, the phase of a digital PLL 3 is lagged, and since the reproducing clock is lagged when it is lower, the phase of the digital PLL 3 is advanced. Namely, by obtaining a rising time and a falling time, a phase difference between the phases of the clock of the receiving data and the reproducing clock can be obtained. Thus, the reproducing clock is always made into the phase with a few errors. |
