| 摘要 |
1. A method of producing an integrated circuit comprising the following successive stages : a) formation of a thin insulating layer (20), constituting the gate insulator of a field effect transistor, in an active zone (A) on a substrate of monocrystalline silicon (10) having a first king of conductivity ; b) etching of the insulating layer (20) to bare the monocrystalline silicon in the contact zones between the source and drain regions and the corresponding electrodes ; c) uniform deposition of a metal silicide (25) over all the substrate, the silicide resting on the gate insulator where it is present and coming into direct contact with the monocrystalline silicon over the remainder of the active zone ; d) deposition of a photosensitive layer (32) suitable to resist the materials for etching the silicide and suitable to serve as a mask holding back the impurities during an operation of implanting impurities ; e) photoetching of the photosensitive layer to produce a resin pattern comprising a portion of resin (29) above the gate insulator, this portion corresponding to the pattern of the gate to be made, and portions of resin (31, 33, 39) defining a source electrode, a drain electrode and interconnections, the resin being removed along the edges of the gate above the active zone and remaining above the silicide in the portions of the active zone where the silicide is in contact with the monocrystalline silicon ; f) etching of the silicide where it is not protected by resin ; g) implantation of ionic impurities to define regions of source (14) and drain (16) ; h) removal of the resin ; i) annealing of the substrate. |
