| 发明名称 |
ARITHMETIC OPERATION UNIT AND ARITHMETIC OPERATION CIRCUIT |
| 摘要 |
In an arithmetic operation unit (103) comprising at least a group of registers (400) and an arithmetic operation circuit (403), bipolar transistors (512, 1011, 1411, 2006, 2008) and field effect transistors (500, 503, 504) mixedly exist. |
| 申请公布号 |
EP0152939(A3) |
申请公布日期 |
1989.07.19 |
| 申请号 |
EP19850101766 |
申请日期 |
1985.02.18 |
| 申请人 |
HITACHI, LTD. |
发明人 |
MAEJIMA, HIDEO;HOTTA, TAKASHI;MASUDA, IKURO;IWAMURA, MASAHIRO;KURITA, KOUZABUROU;UENO, MASAHIRO |
| 分类号 |
G06F5/01;G06F7/50;G06F7/508;G06F13/40;G06F15/78;(IPC1-7):G06F7/48 |
主分类号 |
G06F5/01 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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