发明名称 BUFFER CIRCUIT
摘要 PURPOSE:To increase the buffer operating speed and to reduce the power consumption by decreasing the state transition time while an excess change in a gate potential of an output drive MOS transistor(TR). CONSTITUTION:When an input level transits to a high level, a logic circuit NOR 1 is inverted and a MOS TR MN02 is conductive. The stored charge of a parasitic capacitor C02 is discharged via the TR MN02. Let a source-gate voltage to make a TR MN03 conductive be VTN03, then when the level at a point N04 is below the potential VTN03, the TR MN03 is cut off. Moreover, the stored charge of the parasitic capacitor 01 is discharged via the TR MN01. The level at a point N03 is brought into a potential slightly higher than a potential (Vdd-VTP03). Thus, the time required to reach a level below the level (Vdd-VTP03) is short and the TR MP03 is conductive. Thus, a current flows from the voltage Vdd to the load via the TRMP03 and the level of the capacitor C01 rises.
申请公布号 JPH01181223(A) 申请公布日期 1989.07.19
申请号 JP19880005754 申请日期 1988.01.13
申请人 NEC CORP 发明人 KOGA HIROSHI
分类号 H03K17/04;H03K17/687;H03K19/017;H03K19/0185 主分类号 H03K17/04
代理机构 代理人
主权项
地址