发明名称 |
Address translation circuit including two translation buffers |
摘要 |
An address translation circuit for translating a logical address into a physical address in a computer system using a virtual storage method includes two high-speed buffers (TLB's) for an instruction and an operand, respectively. One of the buffers is selected for use at the time of a memory access depending on a signal supplied from a processing unit to indicate whether the memory access is related to an instruction cycle or an operant cycle. This configuration enables a high-speed address translation without lowering the TLB hit rate and without increasing the amount of the hardware components.
|
申请公布号 |
US4849876(A) |
申请公布日期 |
1989.07.18 |
申请号 |
US19870029161 |
申请日期 |
1987.03.23 |
申请人 |
HITACHI, LTD. |
发明人 |
OZAWA, KOJI;ARAOKA, MANABU;TAKAYA, SOICHI |
分类号 |
G06F12/10 |
主分类号 |
G06F12/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|