| 摘要 |
A symbol timing recovery circuit with a clock synchronization loop for variable rate data signals utilizes a frequency synthesizer for setting the frequency of the recovered clock signal. The received data signal, representing the modulating waveform of a transmitted modulated wareform, is estimated by passage through a data filter and sampling comparator sampled by the recovered clock. The received data signal is also delayed and multiplied by the time derivative of the estimated data signal to produce an error signal representing the difference between the incoming data rate and the output of a narrow pull range voltage controlled oscillator, VCO. The error signal is input to the VCO to correct the VCO output. A programmable frequency synthesizer provides timing signals having a range of the symbol rate divided by n. The VCO output is mixed with the frequency synthesizer output and the sum signals removed by a low pass signal to produce the difference signals which will correspond to the clock signal of the data signal.
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