| 摘要 |
PURPOSE:To reduce the dissidence detection time at change back by making a bit phase matching signal discordance depending on a released signal controlling signal branch from a standby line to an active line. CONSTITUTION:A data signal 11 given to a standby line is compared with a data signal 12 given to an active line by a comparator circuit 102 via a switching circuit 101 controlled by a signal branch control circuit 13. Based on the result of comparison, an R-S FF 201 reaching a difference logic state by the output of the 1st and 2nd count circuits 103, 104 in response to the number of times of coincidence and discordance respectively over each threshold value is set/reset and a phase coincident/discordance signal 18 is outputted. the FF 201 is reset by the release of the signal 13, the discordance detection time at changeover back is reduced not through the circuit 104 and even under the state that the line switching is frequent in same active line due to fading or the like, the total switching time is reduced and hitless switching is applied. |
