| 摘要 |
<p>PURPOSE:To decrease energy consumption of the title circuit being in a stand-by state by causing the oscillating frequency of a clock pulse oscillating means to be low while a synchronous logic circuit is in the stand-by state. CONSTITUTION:The logic circuit executes a logic processing with synchronizing to a clock pulse from an oscillating means 20 which is composed of an oscillating circuit 1 and a dividing circuit 3. The dividing circuit 3 extracts a standard clock signal CLKA from a terminal QA to supply to a line 4, and the signal is fed to an AND gate 5. Then, a low speed clock signal CLKB is extracted from a terminal QB and fed to the AND gate 5. The logic circuit executes back-up processing such as the reception of an input or a time processing but while in the standy state in which the original processing is not executed, the processing can be executed at low speed clock since the processing quantity is small. The higher a clock frequency becomes, the larger the energy consumption quantity becomes and the narrower the operating voltage range of the logic circuit becomes. Thus, AND gates 5 and 7 are selected through an FF8, and during in the stand-by state, the processing is executed with use of the low speed clock signal CLKB. Then, the energy consumption quantity is decreased.</p> |
