| 摘要 |
PURPOSE:To eliminate an interference in the layout between bit lines and to reduce the pitch between the bit lines by a method wherein the main parts of active regions are prevented from becoming parallel even with either of word lines and the bit lines, which intersect orthogonally each other. CONSTITUTION:Active regions 1.1 are arranged in such a way as to form 45 degrees to word lines 1.2 and bit lines 1.4 and parts only, at which contact holes 1.5 of a memory part are opened, of the regions 1.1 are arranged in parallel to the bit lines 1.4. Moreover, the active regions are arranged in such a way that their main parts intersect orthogonally 4 active regions 1.1 adjacent to the active regions 1.1. When a lattice is made of the lines 1.2 and the lines 1.4 in such a way, a pair of diffused layers at the regions 1.1 expose their surfaces on valleys which are made of the lines 1.2 and 1.4. lower electrodes 1, 6, 5 and 9 of a storage capacitor part are formed on these layers and after these electrodes are processed, a capacitor insulating film 5.10 is formed, a plate electrode 5.11 is formed thereon and an Al wiring is wired on this electrode 5.11 through an interlayer insulating film 5.12. |
