| 摘要 |
PURPOSE:To achieve a reduction in a test time, by a method wherein a high power source voltage is applied to a semiconductor device exceeding a preset prescribed voltage to maintain the device in standby and the, a test signal is supplied with the application of a lower power source voltage than the prescribed value. CONSTITUTION:It is assumed that a recommended operating power source voltage of a DRAM composed of one MOS transistor and one capacitance is set in a range of V1-V2. In the execution of a test, first, a voltage VH higher than the voltage V1 is applied to a semiconductor memory and the memory is maintained for T0sec in standby. The time T0sec is set enough to store a voltage in a floating node. But as a sufficiently higher voltage than the voltage V1 is set as applied voltage, the storage of the voltage is accelerated significantly. Then, after the storage of an electric charge with the standby state, a lower voltage VL is applied than the voltage V2 on the lower level side as power source voltage to be applied. Under such a condition, a test pattern is written and further, the memory contents are read out to judge the propriety of the memory cells, thereby enabling a reduction in a test time. |
