| 摘要 |
<p>PURPOSE:To make compatible the flexibility of a line lock mode, the facilitation of a memory practical application, the stability of the clock of a burst lock mode and a low jitter characteristic by providing a selecting circuit to output selectively the field filter output of a horizontal phase synchronizing circuit and a zero data output. CONSTITUTION:At the time of a TV mode, zero data are selected by a selecting circuit 23, added to an adder circuit 16 and a fixed value is given to a digital oscillating circuit 17. On the other hand, since the output of a loop filter 8 is added through a D/A converting circuit 24 to a voltage control crystal oscillating circuit 18, the output frequency of the digital oscillating circuit 17 is in proportion to the crystal clock and consequently, controlled by the output of the loop filter 8. Thus, at the time of the standard TV signal, the burst lock mode is obtained and a stable clock with a small quantity of jitters can be reproduced.</p> |
