发明名称 INTEGRATED LOGIC CIRCUIT INCORPORATING A MODULE WHICH GENERATES A CONTROL SIGNAL THAT CANCELS SWITCHING NOISE
摘要 <p>INTEGRATED LOGIC CIRCUIT INCORPORATING A MODULE WHICH GENERATES A CONTROL SIGNAL THAT CANCELS SWITCHING NOISE A circuit having reduced susceptibility to noise includes a plurality of drivers coupled to a current bus; each driver receives a logic signal on a control terminal and operates to pass a large current when the logic signal is a one and pass a small current when the logic signal is a zero; the current bus has a parasitic inductance which generates a noise signal when the logic signals switch; noise on the current bus is parasitically coupled to the control terminal of each driver; and a plurality of noise reducing modules respectively couple to the control terminal of each driver and a common bus. Each module that receives a switching logic signal generates a control signal on the common bus that is similar in shape and opposite in polarity to the noise signal; and each module that does not receive a switching logic signal couples the control signal from the common bus to the control terminal to which it is connected.</p>
申请公布号 CA1257342(A) 申请公布日期 1989.07.11
申请号 CA19850498463 申请日期 1985.12.23
申请人 UNISYS CORPORATION 发明人 GAL, LASZLO V.
分类号 H03K17/16;H03K19/003;H03K19/086;(IPC1-7):H03K19/00 主分类号 H03K17/16
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