发明名称 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE |
摘要 |
PURPOSE:To reduce current consumption and to prevent a voltage drop during a write operation by a method wherein a memory cell between a selective cell and a bit line is turned on and a selective write operation is executed by using a tunnel of an electric charge between a semiconductor region of a first conductivity type and a floating gate. CONSTITUTION:A NAND cell is constituted in such a way that two or more cells having a floating gate 4 and a control gate 6 are connected in series so as to use a source-drain diffusion layer 9 in common; a memory array is constituted by arranging the NAND cell in a matrix form. The memory cells execute a write operation by tunneling an electron between the floating gate 4 and a substrate 1 where a well 1' has been formed. That is to say, an electron of collected bits is extracted collectively from the floating gate 4 to the well 1' and the bits are erased; then, the electron is injected selectively from a bit line to the floating gate 4. Because the write operation is executed not by injecting a hot electron but by using a tunnel, current consumption is reduced; a voltage drop can be prevented. |
申请公布号 |
JPH01173654(A) |
申请公布日期 |
1989.07.10 |
申请号 |
JP19870329781 |
申请日期 |
1987.12.28 |
申请人 |
TOSHIBA CORP |
发明人 |
SHIRATA RIICHIRO;ITO YASUO;MOMOTOMI MASAKI;OUCHI KAZUNORI;MASUOKA FUJIO;KIRISAWA RYOHEI |
分类号 |
G11C17/00;G11C16/04;G11C16/16;H01L21/8246;H01L21/8247;H01L27/112;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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