| 摘要 |
PURPOSE:To exhibit high speed performance by equipping a first differential amplifier, which is composed of an MOS transistor, and a second differential amplifier, which forms a pair with the first differential amplifier, to obtain a bipolar transistor, in which first and second output nodes are connected to respective bases, and causing the load capacity of the first and second output nodes to be equal. CONSTITUTION:A differential amplifier 1 connects pchMOS elements Q1 and Q2, nchMOS Q3 and Q4 of a driver and an nchMOS Q5 for activation in a prescribed way. A second differential amplifier 2 connects npn bipolar elements T1-T4 and pchMOS Q6 and Q7 in the prescribed way. For a bit line sense amplifier, just after the rising of a clock phi, output nodes B1 and B2 of the differential amplifier 1 once falls a potential and with after that, the B1 goes to be the low potential and the B2 goes to be the high potential in correspondence to bit line information. With receiving this change of the output, in the differential amplifier 2, an output code C1 goes to be the high potential and a C2 goes to be the low potential. In this process, since the load capacity of the output nodes B1 and B2 are equal, without reading the reverse data of bit line data, normal sense operation is executed and the high speed can be exhibited. |
