TIME-DELAYED RELAY

摘要

The relay is drived with certain time delay at on/off operation for preventing the damage caused by over current. An inverting buffer output is applied to an input terminal of "on" delay time setting circuit (1) which output is connected to a R-S Flip-flop (U3) input terminal (R). A shunted output of the inverting buffer is connected to the "off" delay time setting circuit (2) which output terminal is connected to the R-S Flip-flop (U3) input terminal through a non- inverting buffer. The output terminal of the R-S flip-flop is connected to a transistor (TR1) for driving a relay (RY1).