| 摘要 |
PURPOSE:To prevent loss of a clock output or production of extreme change even if a transmission fault takes place by providing plural clock extraction circuits corresponding to plural transmission lines, correcting a phase difference caused due to a delay time difference of the transmission line to be a prescribed value or below and synthesizing the result. CONSTITUTION:Clock extraction circuits 61, 62, 63 consist of a narrow band filter, or a narrow band filter and a phase synchronizing oscillation circuit, extract clock signals 71, 72, 73 from input signals 57, 58, 59, give them to delay compensation circuits 96, 97, 98 respectively and send transmission signals 79, 80, 81 to the frame synchronizing circuits 66, 67, 68. The frame synchronizing circuits 66, 67, 68 extract frame synchronizing signals 85, 86, 87 and send them to a delay difference detection circuit 88. Then delayed correction clock signals 101, 102, 103 are sent to a synthesis circuit 105, from which an output signal 107 is sent. |
