发明名称 BURST RETIMING SYSTEM
摘要 <p>PURPOSE:To absorb a burst position error of a wide range by using plural elastic buffers applying retiming from a burst clock to a system clock in parallel. CONSTITUTION:The same two elastic buffers 101, 102 are connected in parallel, an input data is written alternately by using write clocks WCLK1, WCLK2 with different phase generated in response to the burst clock from the 1st clock controller 11, the data in the elastic buffers 101, 102 is read alternately by using read clocks RCLK1, RCLK2 with different phase generated in response to the system clock from the 2nd clock controller 12, it is selected by a selector 13 and outputted. Then even if a burst location error of a reception burst is large to absorb the burst location error thereby applying retiming to an ideal frame.</p>
申请公布号 JPH01171337(A) 申请公布日期 1989.07.06
申请号 JP19870335171 申请日期 1987.12.25
申请人 FUJITSU LTD 发明人 KURODA YUJI;TANI HISAMICHI
分类号 H04J3/06;H04B7/15;H04L7/00 主分类号 H04J3/06
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