| 摘要 |
PURPOSE:To compose a PLL circuit corresponding to the modes of both sides by switching decoders to a reproducing device to have different speed modes. CONSTITUTION:When a phase difference signal between an input signal and a PLL clock is detected, the phase difference signal is decoded by first and second decoders 10a and 10b, and it is loaded as the value of the frequency- dividing ratio of a frequency-divider 12 generating the PLL clock. Here, the first and second decoders 10a and 10b are switched by a data switching device 11 to those in which decoding characteristics are different according to the speed mode of the input signal. For example, in a DAt, the first decoder 10a is selected which corrects the frequency-dividing ratio so as to be made large when a phase dislocating quantity is large and which corrects the frequency- dividing ratio so as to be made small when the phase dislocating quantity is small in a normal mode to execute an ordinary reproduction. Since the fluctuation of the speed is large in a search mode, the second decoder 10b is selected which executes a correction in the frequency-dividing ratio to be approximately proportionate to the phase dislocating quantity. |
