Determination circuit for data coincidence.

摘要

A coincidence determination circuit capable of reducing number of elements by providing a time period during which the coincidence determination is enabled. This coincidence determination circuit comprises, a first comparison unit provided with a plurality of first bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first P-channel transistor (T3-T6) having a gate to which a clock signal is inputted, a second P-channel transistor (T11-T14) having a gate to which reference data of a certain bit is inputted, and a third P-channel transistor (T19-T22) having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third P-channel transistors being connected in series, respective outputs of the first bit comparison units being wired-OR connected to a first output line (N1), said first output line serving to pull its signal level down in response to the clock signal; a second comparison unit provided with a plurality of second bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first N-channel transistor (T7-T10) having a gate to which an inverted signal of the clock signal (CLK) is inputted, a second N-channel transistor (T15-T18) having a gate to which reference data of a certain bit is inputted, and a third N-channel transistor (T23-T26) having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third N-channel transistors being connected in series, respective outputs of the second bit comparison units being wired-OR connected to a second output line (N2), the second output line serving to pull its level up by the inverted signal of the clock signal; and an output unit (2, 3) for producing a coincidence output when the first output line is at a low level and the second output line is at a high level.