| 摘要 |
<p>Herein disclosed is a data processing apparatus (100) such as a pipeline processing microprocessor, in which the content of a subsequent instruction to be fetched from a memory is different depending upon the formation or non-formation of a conditional branch instruction. In order to execute the conditional branch instruction, a micro-ROM contains: a first micro-instruction having an information for a conditional discrimination, an information requesting a branch ready and a subsequent micro-address of an even address; a second micro-instruction having an information requesting a branch and a subsequent micro-address of an odd address; and a third micro-instruction requesting a subsequent instruction decoding. When the branch condition is formed, the even address is outputted from a micro-address generating circuit (115). Before the branch is requested by the second micro-instruction, a micro-address analyzing circuit (130) feeds, if the brach condition is formed, the branch request signal to an instruction fetch unit (101) in response to the even address and the branch ready information of the first micro-instruction so that the time interval between the execution of the conditional branch instruction and the execution of the subsequent instruction can be shortened.</p> |
