| 摘要 |
PURPOSE:To detect a correct arithmetic fault with a small hardware quantity by executing respective arithmetic fault detections of an arithmetic circuit with a time division at every arithmetic circuit. CONSTITUTION:A selecting signal to designate one of arithmetic circuits 10A-10D detecting the arithmetic fault is supplied to a selecting signal path 1 and a selecting circuit 12 is controlled so that the fault detection of four arithmetic results can be successively executed with the time division at every machine cycle 1T. The selecting signal is successively supplied and set to a selecting signal receiving register 2A, and after these selecting signals are decoded successively with a decoder 3, they are successively stored into a final step register 2G. Thus, in respective cycles of the machine cycle, registers 17A-17D are respectively successively selected by the contents of the register 2G, they are compared with the output data of a parity predicting circuit 7 by a parity comparator 13 and then, the fault status of respective arithmetic circuits 10A-10D can be decided. |
