| 摘要 |
A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equation An(t)=An(t-1)(+)[(UxPn)+(DxQn)] where An(t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. Pn represents a product of Ak's for 1</=k</=-1, while Qn represents the product of &upbar& A's for 1</=k</=n-1, where &upbar& Ak is the complement of Ak and Pn and Qn are expressed as the following two equations Pn=An-1An-2 . . . A1 Qn=An-1An-2 . . . A1 which can be written in recursion form as Pn=Pn-1xAn-1 Qn=Qn-1xAn-1 with the initial values P1=1 and Q1=1.
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