| 摘要 |
A reset pulse having a desired pulse width is generated in a reset pulse generating circuit 14 in response to a vertical synchronizing signal selected and outputted from input selecting circuit 13 or a frequency-divided output signal of a vertical count down circuit 11, the vertical count down circuit 11 is reset by the reset pulse, and a vertical driving pulse phi 5 with a predetermined period is generated. Furthermore, phases of the reset pulse and the frequency-divided output signal are compared in a phase comparing circuit 19, a period of a vertical synchronizing signal is determined, and the input selecting circuit 13 and a signal selecting circuit 18 are switched to each other in accordance with the result.
|
