| 摘要 |
An interface circuit conditions TTL logic level signals to be compatible CMOS logic circuits. An inverter (14) is disposed on a CMOS logic circuit chip (10) for receiving TTL logic level signals. The switching voltage point of the inverter is controllable by a bias voltage. A bias generator (12) on the chip produces a bias voltage for the inverter which is compensated for supply voltage, temperature and process variations and which is utilized to stabilize the inverter switching point.
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