Synchronous clock frequency conversion circuit

摘要

A conversion system that provides compatibility between the internal system bus architecture of one computer and an external bus that operates on a different frequency includes a clock logic circuit for generating a clock signal that is synchronized with the internal clock for the computer system. The clock circuit includes a delay line that provides a plurality of phase displaced signals at the operating frequency of the computer system. Each of these phase displaced signals is multiplexed in accordance with the relationship of its phase to that of a signal at the clock frequency of the external bus. By multiplexing the phase displaced signals in the appropriate manner, pulses are generated with a time period corresponding to that of the desired external bus clock frequency.