| 摘要 |
A system for programming an asynchronous logic cell and a two- or three-dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The programming system facilitates the construction of circuits, circuit modules, black box elements and the like, with provision for storing such building blocks in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together. Further, because the array is regular and switch settings can produce logical wires, crossovers, connections and routings running both "horizontally" and "vertically", it is in general possible to "wire around" defective elements. If a large wafer contains defective cells, those cells can simply be avoided and bypassed, with the remainder of the wafer remaining useful. The programming system facilitates the rotation and reflection of blocks, to exploit the symmetry of the array and minimize unproductive cell area. The user is can see a representation of the chip as it is transformed by programming.
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