| 摘要 |
PURPOSE:To attain ease of failure check with a simple test input, by producing an exclusive logical sum between all of output signal group of exclusive logical sum of plural input signals and control input signals, and an input signal for check. CONSTITUTION:In the exclusive logical sum gate group 11 of a combined logical block 1, an exclusive logical sum output group XC between each input signal xi(i=1-n) of an input signal group X=(x1-x2) and a control input signal C is outputted. In an AND gate group 12, the AND between the signal groups X and Xc is outputted and inputted to an exclusive logical sum gate group 13. In the gate group 13, the exclusive logical sum between the output signal group of the gate group 12 and some logical constants y1 and X and Xc is taken, an output signal Z1 is produced. The check of a failure in logical degeneration of the signal line is done easily by taking an output of the gate group 13 as an observing signal. Further, a signal short-circuit failure between lines is detected by taking the exclusive logical sum between the signal group Xc and an input signal y2 for check at a logical block 2 and outputting an observing signal Z2 for check. |
