发明名称 PHASE SYNCHRONIZING SYSTEM
摘要 <p>PURPOSE:To attain phase synchronization between a master station and each slave station without using an ultrahigh speed clock by using a data clock equal to transmission speed as a clock for transmission phase shift and setting the pulse width of a monitor bit to be several times of the data clock period or above. CONSTITUTION:A low speed data clock DCL is used in a phase synchronizing section 40. The pulse width of a monitoring bit M is selected to be several times of the period of the data clock DCL or above, the monitoring bit M is coded via a multiplex section 21, sent to a line T and reaches the master station 1. The phase synchronization by the data clock DCL is only the frame synchronization, but the bit synchronization by a preamble PR is taken under block multiplex. Thus, the phase synchronization is taken between the master station 1 and each slave station without using the ultrahigh speed transmission phase shift clock.</p>
申请公布号 JPH01168135(A) 申请公布日期 1989.07.03
申请号 JP19870325333 申请日期 1987.12.24
申请人 FUJITSU LTD 发明人 AMAMIYA SHIGEO;KOMINE HIROAKI;SHINOMIYA TOMOHIRO;IGUCHI KAZUO;SOEJIMA TETSUO;MURANO KAZUO
分类号 H04L7/00;H04L12/40 主分类号 H04L7/00
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