| 摘要 |
PURPOSE: To simplify the electrical continuity of a doped region with an outside electronic circuit by generating a conductive material along the vertical end of a wafer, and electrically connecting the conductive material with an exposed conductive lead. CONSTITUTION: Grooves 39, 41, 43, and 45 are formed on the opposed surfaces of silicon wafers 35 and 37. Next, silicon dioxide is buried in the grooves 39, 41, 43, and 45. Then, the wafer parts 35 and 37 are connected so as to face to each other, and grooves 42 and 44 in which insulating materials are buried are formed so as to be united. Then, silicon materials are removed in the upper part of the wafer 35 until the insulating materials buried in the insulating grooves 42 and 44 are exposed, and an active integrated circuit is formed on the surface of the wafer part 35 by the formation of doped regions 46. Then, a pattern 48 of a conductive lead interconnects the doped regions 46, and extended along the grooves 42 and 44. An input lead 18 and an output led 16 are provided along the insulating grooves 42 and 44 so as to be electrically continued with the active circuit. Then, silicon on the lower face of the wafer 37 is removed by grinding or wrapping, and a chip can be completed by cutting the grooves 42 and 44 from the center.
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