| 摘要 |
<p>PURPOSE:To establish the synchronization even if any phase difference exists between an external clock and an internal clock by providing a FF set by an AND signal between a clock whose pulse width is twice that of the external clock and the internal clock. CONSTITUTION:The FF 25 is set/reset by an AND signal between clocks 31, 32 formed by the external clocks 31, 32 and the internal clock. In such a case, the trailing edge of an output signal 35 of the FF 25 is delayed a little from the leading edge of the internal clock due to a delay in the FF 25 or the like. Since the leading edge of the internal clock exists in the pulse width (T) time of the output signal 35 without fail, an output signal 36 of a FF 26 rises synchronously with the leading edge of the internal clock and the pulse width reaches T. The output 33 of the FF 21 is selected by the signal 36, the selected signal 37 is segmented by the trailing edge of the internal clock to obtain an output data.</p> |
