| 摘要 |
PURPOSE:To reduce the number of wiring from first and second board to a third board, by a method wherein, when a signal from a first circuit unit is inputted to a third circuit unit, a clock signal is generated, and in an EOR circuit the signal from the first circuit unit is EORed with a signal from a second circuit unit. CONSTITUTION:A clock signal CLK is periodically generated on a third board 3 when an enable signal e1 has a high level '1'. At this time, the levels of signals A, B on a first board 1 are inputted to one-side inputs of EOR circuits 38, 39 while being held by a flip flop 36 of the third board 3. When an enable signal e2 has a high level '1', the levels of signals C, D on a second board 2 are inputted to the other-side inputs of EORs 38, 39 of the third board 3, and the both are EORed. Accordingly, when a signal on the first board 1 is EORed with a signal on the second board 2 on the third board 3, the output terminal of the first board 1 and the output terminal of the second board 2 to be EORed with each other are previously connected through a wired OR, and the signals can be transmitted from this wired OR up to the input terminal of the third board 3 through one wire. |
