发明名称 BANK MEMORY CONTROL SYSTEM
摘要 PURPOSE:To prevent the erroneous access to bank areas, by selcting a specific bank area independently of contents of the bank register in case of performing DMA. CONSTITUTION:When the control part performs DMA to the main storage part, the DMA signal becomes ''H'', and the address designation for decoder output addresses E000-FFFF input through address bus 7 is supplied to bank area MEM1 through AND gate AG3 and OR gate OG1. That is, bank area MEM1 is accessed certainly without the influence of contents of bank register 1 for switching of bank areas.
申请公布号 JPS56153459(A) 申请公布日期 1981.11.27
申请号 JP19800056808 申请日期 1980.04.28
申请人 FUJITSU LTD 发明人 SATOU AKIRA;KUBOTA SHINICHI;MIYAMOTO TOSHIHIRO;MURATAKA HISAO
分类号 G06F12/06;G06F13/28 主分类号 G06F12/06
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