| 摘要 |
PURPOSE:To execute a test at speed higher than the highest action speed of fail memories by executing repeatedly the writing of defective data, etc., of a tested IC memory to an N fail memories in turn and reading simultaneously with N pieces of them. CONSTITUTION:Signals whose periods are four times as much as the basic period of the output of a timing generator 1 and whose phases are successively dislocated by one period are generated by a control signal generating circuit 4 and supplied to a write enable generating circuit 10 and write enable signals are supplied to corresponding memory circuits 91-94 for storing the defective data. A pattern generating circuit 3 generates a pattern whose data changes at basic period and supplies it to a tested IC memory 5. The output of the tested IC memory 5 is compared with the output of a comparison pattern generator 2 by a comparator 6 and its output is successively supplied to the memory circuits 91-94 for storing the defective data. On the other hand, the reading out of the memory circuits 91-94 for storing the defective data is executed all simultaneously with the four pieces and their outputs are composed and outputted. |
