| 摘要 |
1. An electrically reprogrammable non-volatile memory, formed in lines and columns of memory points each comprising a floating gate transistor (T1) and two selection transistors (T2 and T3) receiving a common selection signal on their connected gates (GSi), on of them (T2) being connected between a first column conductor (Dj) and the drain of the floating gate transistor, and the other (T3) being connected between a second column conductor (GCj) and the floating gate transistor, the sources of the floating gate transistors of the same column being connected together by means of third column conductors (Sj), the memory further comprising a line decoder adapted to apply a selection voltage to a given line conductor (GSi) connecting the gates of all the selection transistors of that line, this memory being of the sort in which, during a writing phase, a zero voltage is established on the first column conductors (Dj) of the columns corresponding to the memory points are not selected, the second column conductors (GCj) corresponding to these same columns being left a high impedance or brought to zero voltage, characterized in that it comprises a column decoder connected independently and directly to each of the column conductors and adapted to establish simultaneously, during a single writing phase, a writing potential difference (VH) between the first and the second column conductor, for all the columns corresponding to memory points selected, this potential difference being of a first sign for writing a mch>Omch< in a given memory point and being of the opposite sign for writing a mch>1mch< in another given memory point. |
