发明名称 PHASE LOCKED LOOP OSCILLATOR
摘要 PURPOSE:To accurately decide the phase of an output signal for an input signal by constituting a system so that a loop gain in the neighborhood of the center of phase comparison range can be heightened sufficiently equivalently. CONSTITUTION:The title oscillator is provided with a phase comparator 10, a voltage controlled oscillator 40, a phase shifter circuit 50, a phase comparator 11, a voltage adder circuit 20, and a low-pass filter 30, When the output frequency of the voltage controlled oscillator is lower by (f) than an input frequency, it is necessary to heighten a control voltage by DELTAV to set the output frequency equal to the input frequency. In such a case, since a control voltage characteristic is shown as the one in figure, the control voltage exceeds P1 if the phase of the output signal lags by a little for that of the input signal. Here, by constituting two phase comparators 10 and 11 and the voltage adder circuit 20 so as to establish relation P1>DELTAV, the control voltage over the control voltage DELTAV required for the phase locking for the lowering by DELTA of the frequency is added on the voltage controlled oscillator 40. In such a way, it is possible to decide phase relation between the input signal and the output signal strictly.
申请公布号 JPH01165226(A) 申请公布日期 1989.06.29
申请号 JP19870322935 申请日期 1987.12.22
申请人 NEC CORP 发明人 MUTO HIROSHI
分类号 H03L7/087;H03L7/08 主分类号 H03L7/087
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