发明名称 DIGITAL TV SIGNAL PROCESSING CIRCUIT
摘要 <p>PURPOSE:To reduce the scale of the hardware of a whole system by correlating a phase locked loop(PLL) circuity and automatic color controlling(ACC) circuit to each other. CONSTITUTION:The phase error detection at a PLL circuit and burst peak detection at an ACC circuit are constituted in common. Namely, latching circuits 56 and 61 make latching operations at the leading timing of burst gate pulses. The latching operations are carried out at every 1H. Therefore, the output of the latching circuit 56 becomes the phase error signal of the PLL circuit 59 which is zero and the output of the latching circuit 61 becomes the burst peak of the ACC circuit 46 and the circuit 46 outputs a peak value P0. Since the phase error information of burst signals and sampling clocks and burst peak value can be obtained, the scale of the whole circuit can be reduced.</p>
申请公布号 JPH01165289(A) 申请公布日期 1989.06.29
申请号 JP19870323092 申请日期 1987.12.21
申请人 TOSHIBA CORP;TOSHIBA AUDIO VIDEO ENG CORP 发明人 SATO KOICHI;YASUKI SEIJIROU
分类号 H04N9/68;H04N9/45;H04N11/04 主分类号 H04N9/68
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