| 摘要 |
PURPOSE:To reduce the lead time significantly by a method wherein, after 2nd insulating films are formed on the side walls of gate electrodes, the insulating films on the side walls of the specific gate electrode are removed at least selectively and impurity ions are implanted into a semiconductor substrate. CONSTITUTION:Element isolation insulating films 2 and gate insulating films 3 are formed on a substrate 1 and, after polycrystalline Si is deposited and etched to form gate electrodes 6, first insulating films 8a are formed. Then impurity ions are implanted into source and drain regions to form low concentration impurity regions 7. Then SiO2 is deposited over the whole surface and etched back to form second insulating films 8b on the side walls of the gate electrodes 6. Then peripheral circuit parts are covered with resist 4 and the second insulating films 8b on the side walls of the gate electrodes 6 of a memory cell part are selectively removed by wet-etching. After resist 4 is applied and patterned, punch through is produced in the source and drain regions by ion implantation and a thermal oxidation. |
