| 摘要 |
<p>A Switched Capacitor circuit implemented by various hardware reduction techniques offering significant savings in chip area and power dissipation. The reduction techniques include Pole Sharing methodologies for multiplexed and unmultiplexed circuits; Full-Multiplexing which combines Time-Sharing and Time-Division-Multiplexing applied to circuits realized as a summation of poles; Capacitor Sharing techniques; a Full-Wave Rectifier having elements able to be shared in a Time-Multiplexed application and a DC offset reduction technique which minimizes additional hardware.</p> |
