Shared memory interface for a data processing system.

摘要

The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended.