| 摘要 |
<p>A clock regenerator (24) generates a clock Co synchronized with an input data pattern (Di) and a data pattern generator (26) generates a reference data pattern (Dr) in synchronization with the clock Co. The reference data pattern and the input data pattern are compared by a data disagreement detector (21) to detect disagreement therebetween. The disagreement detection signal (Pe) thus obtained is frequency divided by a 1/m-frequency divider (32) and its frequency-divided output is further frequency divided by a 1/n-frequency divider. The frequency-divided output of the 1/n-frequency divider is provided to a bistable flip-flop (34), placing it in one stable state. The logical sum of the output of the flip-flop in the one stable state and the 1/m-frequency divider is obtained, as an inhibit pulse, by gate means (41), and the inhibit pulse is applied to an AND gate (42) to inhibit the passage therethrough of the clock Co to the data pattern generator, delaying the generation of the reference data pattern in the data pattern generator. The 1/m-frequency divider, the 1/n-frequency divider and the flip-flop are reset every k pulses of the clock Co.</p> |
