Complementary metal oxide silicon (CMOS) device structure.

摘要

A sub-surface interconnection structure for coupling an n-type diffusion (62) to a p-type diffusion (54). The structure is a conductor-filled trench (100) disposed between the diffusion regions. The trench has a thin dielectric layer (110) on its sidewalls and bottom. The conductor (120) within the trench contacts the diffusion regions. Parasitic device formation between the diffusion regions is suppressed because the trench provides a parasitic gate that is shorted to the parasitic source regions (i.e., the coupled diffusion regions). Moreover, the trench provides an enlarged contact to the coupled diffusion regions for the subsequently-applied metal layer.