Method of selective via-hole and heat sink plating using a metal mask

摘要

A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of: (a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side; (b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur; (c) forming via-holes through said wafer; (d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and (e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.