| 摘要 |
<p>PURPOSE:To miniaturize an asynchronous speed converting circuit by writing the input data into a RAM synchronously with a write signal and simultaneously obtaining the output data synchronous with a read control signal. CONSTITUTION:An address supplying means 121 supplies a write address to a RAM 111 synchronously with a write signal and at the same time supplies a read address also to the RAM 111. A write means 131 supplies the received input data to the RAM 111 for writing while the write address is supplied to the RAM 111 from the means 121. A read control means 151 supplies a read control signal having the same cycle as the read signal to a read means 141 in accordance with both write and read signals so that the timing never overlaps the data writing action of the RAM 111. Thus the means 141 reads data out of the RAM 111 synchronously with said read control signal to obtain the output data. In such a way, a compact speed converting circuit is obtained.</p> |
