| 摘要 |
A switching power supply includes push-pull power switches driven by first and second conjunction gates. The conjunction gates are coupled to receive the output of a flip-flop, together with the antiphase outputs of a binary divider which divides down the output of the flip-flop. The flip-flop is driven recurrently by sync to enable one of the conjunction gates, and the binary divider steers the enablement alternately. When the output voltage or current crosses the design threshold, a comparator is triggered to produce a shut-down signal which is applied to the reset input terminal of the flip-flop to reset it. Delay in the flip-flop is avoided by also applying the shut-down signal to the conjunction gates. The maximum possible duty cycle is extended by initiating switch conduction at a predetermined short time after initiation of the sync pulse.
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