发明名称 CARRIER LOCK DETECTION CIRCUIT
摘要 PURPOSE:To attain the synchronizing detection in a short time with simple circuit constitution by integrating a phase error detection signal detected by a demodulation circuit and comparing its integration value with a prescribed threshold value so as to detect the synchronization. CONSTITUTION:The frequency sweep in the demodulation circuit 101 is implemented when the frequency fluctuation range exceeds the synchronization enable range, and a phase error signal being an output of a phase error detection circuit 103 becomes a beat signal in response to the frequency deviation in the synchronization enable range and the frequency fluctuation range in case of the implementation of the frequency sweep. Thus, a signal being the result of integrating the beat signal at a prescribed time interval becomes a beat signal and the amplitude is larger as the frequency deviation is smaller. Then the signal integrated by an integration device 107 is outputted to a comparator circuit 108. The comparator circuit 108 is configurated such that it compares the relation of quantity between the output level of the integration device 107 and a preset threshold level and outputs the result of comparison as a signal discriminating the propriety of consecution of the frequency sweeping of the output of a loop filter 105 to a control circuit 109.
申请公布号 JPH01160239(A) 申请公布日期 1989.06.23
申请号 JP19870317508 申请日期 1987.12.17
申请人 NEC CORP 发明人 IWASAKI GENYA;OTANI SUSUMU
分类号 H04L27/227;H04L27/22;H04L27/38 主分类号 H04L27/227
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