| 摘要 |
PURPOSE:To shorten the channel of a FET and increase the working speed of the FET by forming a junction at an inclination close to verticality (a vertical type FET) and controlling gate length by controlling the thickness of a growth layer. CONSTITUTION:An n<+>-GaAs layer 2 and a p<+>-GaAs layer 3 are grown in succession on an SI-GaAs substrate 1 by using an MBE method. Silicon is employed as an n-type dopant and beryllium as a p-type dopant. A groove 4 is formed through chemical etching employing a sulfuric acid group etchant through normal lithography. The groove 4 is coated by using the MBE method, and an n-GaAs layer 5 is grown. Electrode-forming regions in each layer are exposed and respective electrode is shaped, thus acquiring a FET having a short channel and operating at high speed. |
