| 摘要 |
<p>PURPOSE:To reduce skew between clock pulses by supplying a clock pulse to respective second clock pulse supplying circuit in semiconductor areas divided into plural parts from a first clock pulse supplying circuit formed in the center of a semiconductor chip. CONSTITUTION:The first clock pulse supplying circuit MCG is arranged in the center part of an LSl consisting of four circuit areas B1-B4 divided quarterly. Next, the clock pulses having different phases are supplied from input circuits INC1 and INC2 having equal wiring length to the MCG. Also, the second clock pulse supplying circuits LC1-LC4 are provided in the center parts of the divided circuit areas B1-B4, and plural number of radiant fan-out are attached on each circuit, and it is set so as to take an equal load. In such a way, since the same path from the input of the clock pulse to the final logic circuit can be realized, it is possible to suppress the skew between the clock pulses with each other.</p> |
