| 摘要 |
<p>PURPOSE:To realize a timing check with high accuracy approximate to that of a real product by calculating the timing for each transistor TR with consideration given to the total gate capacity of the TR of the next stage, the total wiring capacity/resistance up to the TR of the next stage, the power supply voltage, the ambient temperature, each process parameter, etc. CONSTITUTION:Data stored in files 3-7 are supplied to a calculation formula and a computer 1 calculates the timing (delay time) of a circuit. A net list added with said calculated timing is outputted from a simulator device 8. In other words, the delay time is added to each TR in the net list for logical simulator. When this delay time is calculated, the total gate capacity of the TR of the next stage is taken into consideration together with the total wiring capacity/resistance up to the TR of the next stage, the power supply voltage, the ambient temperature, each process parameter, etc. Thus it is possible to perform the timing check with high accuracy approximate to that of a real product.</p> |
