| 摘要 |
The present invention generates a data clock for data processing circuitry by developing an optimum locally generated clock signal which is selected with each received data message. This is achieved by utilizing a local crystal clock which serves as an input to a multiple active parallel tap delay line. A register has the various delay signals input to it and a window generator strobes the inputs to the register so as to process the strobed levels of the various delayed clock signals. This is done to detect a level transition in any of the clock phases. Gating circuitry then chooses an optimum clock phase which has undergone a transition in a desired direction during the time window when the various clock phases were strobed. As a result of the present invention, utilized bandwidth may be increased and data distortion is minimized so that the number of stations connected to a data bus provided with the data clock of the invention may be increased substantially.
|
